1. Field of the Invention
The present invention relates to circuitry for generating power-on reset signals for transmission to integrated circuit systems. In particular, the present invention relates to a power-on reset circuit that operates to hold off power-on reset until the high-potential power supply rail reaches a defined potential. More particularly, the present invention relates to power-on reset circuitry that is relatively independent of fabrication and operating temperature vagaries.
2. Description of the Prior Art
Power-on reset circuits are designed to transmit to semiconductor-based systems signals to enable operation of such systems only when a common high-potential power rail reaches a certain minimum potential. These power-on reset circuits may be used to enable "hot" or live insertion of systems or subsystems such as circuit boards that are initially unpowered into extended coupled circuitry that is powered. The power-on reset circuitry is supposed to protect the unpowered system or subsystem from significant initial potential variations that may cause damage or unexpected operational anomalies in the circuitry that is inserted into the active system. In effect, the power-on reset circuit is designed to hold off enabling activation of the subsystem until the power rail potential is suitable for activation of that particular subsystem.
Power-on rest circuits come in a variety of designs. One circuit that has been found to be adequate in prior systems is illustrated in a simplified diagram in FIG. 1. The prior reset circuit includes a voltage divider formed of resistors R10 and R11, wherein R10 is tied to the common high-potential power rail Vcc and R11 is coupled to the common low-potential power rail GND. As the potential of Vcc begins to rise, the output of the circuit at OUTPUT essentially tracks Vcc less the drop across resistor R12. Logic functions coupled to OUTPUT define whether that logic high signal holds off of the powering up of the circuitry to which OUTPUT is coupled. In the meantime, the voltage divider, and in particular the potential at the low-potential node of R10, delays the turning on of pull-down transistor Q1. Only when there is enough current at the base of Q1 will that transistor turn on and thereby pull the potential at OUTPUT down to a logic low level in a manner that enables power-on reset of the circuitry to which OUTPUT is coupled. The resistance values of R10 and R11 define the Vcc potential at which Q1 is turned on and therefore the potential at which the signal at OUTPUT switches.
While the circuitry shown in FIG. 1 works well for circuitry in which relatively large swings in logic levels are acceptable, its design is subject to fabrication variations and temperature changes. That is, variations in resistances and transistor I-C characteristics will change the point at which the potential at Vcc is sufficient to switch the output at OUTPUT. Similarly, wide temperature swings of the type that may be experienced by semiconductor devices will also affect operational response. As a result, it is possible to have the potential at which Q1 is turned on change by 1 volt or more--an unacceptable condition as logic swing requirements become tighter. To an extent, this problem is related to the fact that power-on reset circuits are generally referenced to the Vcc rail rather than the GND rail. It is to be noted that such referencing, as well as the fabrication and temperature sensitivity, can also lead to a change in the reset circuit's ability to provide a power-on signal at a well-defined minimum potential. The result can be undesirable delays in operation of that extended circuitry, particularly when it forms part of a larger operating system.
Therefore, what is needed is a power-on reset circuit that is less dependent on process vagaries and temperature swings than that of prior reset circuits. What is also needed is a power-on reset circuit that is referenced to the more certain low-potential power rail. Further, what is needed is a power-on reset circuit that enables transmission of a power-on signal at a selectable minimum potential of the high-potential power rail and within a more well-defined range of potentials.